Method for Optimizing a 10 Gb/s PCB Signal Launchs

http://www.xilinx.com/publications/magazines/io_01/xc_pdf/p60-69_1io-whi...

The authors of this paper present a method for optimizing the performance of high-speed signal launches onto PCB traces. At a bit rate of 10
Gb/s, signal rise times are typically 30 ps. At these speeds, even small impedance discontinuities can degrade the signal that is launched onto the
PCB. Longer rise times, smaller eye openings and overshoot are among the effects that can be caused by an improperly designed launch. Therefore,
careful design of the launch is essential. While the example used in this paper is the SMA to PCB interface, the method is generic enough to be
applicable to modeling of vias or any other structures that may be part of a channel.